Interlaken is the name of a very picturesque town in Switzerland (pictured), but it’s also the name of the next communications protocol that will be driving a cloud near you! Maybe the fact that Interlaken, the town, sits between two huge lakes in the Alps is what inspired the name of the protocol. Think of the lakes as huge pools of data that needs to move from one lake to another. You get the idea.
Chip-to-chip bandwidth is one of the major bottlenecks in cloud computing as the amount of data that needs to be moved around increases incessantly. Cisco and Cortina Systems recognized the need in 2006 and announced the protocol. The two companies joined with Silicon Logic Engineering (now part of Open-Silicon) in 2007, and put out an Interlaken Technology White Paper.
The whitepaper summarizes the protocol, “Interlaken is an interconnect protocol optimized for highbandwidthand reliable packet transfers. It uses bundles of serial links to create a logical connection between components with multiple channels, backpressure capability, and data-integrity protection to boost the performance of communications equipment.”
So, if you were to design and verify an Interlaken core on your next chip integration. Where would you get your IP core, and where would you get your Verification IP (VIP)? After looking around, this is what we found.
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| Interlaken Controller IP Core |
| Open-Silicon’s Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI…more |
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| Interlaken IP Core |
| Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 150Gbps…more |
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| Altera’s Interlaken intellectual property (IP) continues to scale with today’s demand for more bandwidth and higher performance needs…more |
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| Interlaken Controller IP Core |
| Flowgic’s Interlaken IP core is an efficient implementation of Interlaken Protocol version 1.2. Interlaken IP core is designed for flexibility, robustness, scalability and is available in 64(10-20 Gb/s), 128(20-40Gb/s), 256(40-80Gb/s) and 384(80-120Gb/s) bit datapath variants…more |
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| Interlaken IP Core |
| The Interlaken is a high speed, narrow, channelized and highly configurable chip-to-chip interface protocol. It offers programmable burst sizes, per-channel backpressure, source-asynchronous nature and scalability…more |
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| 3G to 600G Interlaken ILK and ILA IP Core |
| Tamba offers industry’s lowest latency, power, and size solution for the Interlaken communication protocol. The Universal Interlaken IP Core can be customized from 1 Gbps to 600 Gbps and targeted to both FPGA and ASIC platforms…more |
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| XCI4FIC 100G Interlaken Fabric Interface Core |
| The Xelic 100G Interlaken Fabric Interface Core (XCI4FIC) provides the flexible transport of channelized signals for both segment mode and packet mode transmission formats with configurable lane number support. Flow control is provided for both in-band and out-of-band methods with optional automatic and override insertion capability…more |
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| Interlaken VIP |
| The Interlaken Verification IP is compliant with 1.2 specifications and verifies Interlaken interfaces of designs Interlaken Interface. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment…more |
| Rockfish Technologies |
| INTERLAKEN ASIC IP |
| The Optimized Interlaken Protocol IP block from Rockfish Technology supports all the published extensions and interoperability recommendations from the Interlaken Alliance including…more |
| Rockfish Technologies |
| INTERLAKEN VERIFICATION IP |
| The Vermilion BFM bridges the gap between the user’s testbench and an Interlaken Device Under Test (DUT). Vermilion BFM Egress Interlaken Framing Layer Features…more |
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